DFT Staff Engineer

hace 3 semanas

Guadalajara, México Synopsys A tiempo completo

DFT Staff Engineer

Job Description and Requirements

We’re not just a traditional EDA & IP company you’re familiar with. We understand how the SoCs we help create are used, and work with our partners to deliver world beating products.

At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The Cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Digital Team is looking for a skilled Senior Design For Test (DFT) Engineer to join our talented team.
If you are an experienced Engineer on DFT and/or Verification area and eager to collaborate with experts in dynamic digital design using the latest process technologies this can be a perfect opportunity for you.

DFT Staff Engineer

Job Description:

  • Do SCAN and MBIST Insertion.
  • Design, implement and verify test methodologies for IP interface subsystems and complex SoCs
  • Analyze RTL Scan-readiness.
  • Perform ATPG and coverage debugging.
  • Perform pattern verification with and without timing back annotation.
  • Analyze and debugging failures to establish root-cause
  • Validate and test state-of-the-art DFT flows and methodologies.
  • Make DFT integration guideline to SoC level


Requirements:
  • Experience with DFT flow, including DFT design, implementation, verification, and testing.
  • Good knowledge of scripting languages, such as TCL/Perl and description languages such as Verilog.
  • Skill with design tools: Synopsys Design Compiler, VCS, Formality, TetraMAX
  • Familiar with Silicon testing.
  • Great team player, willing to support others
  • Good English communication both verbally and writing skills.
  • Self-motivated and highly enthusiasm in technology and solving problems

Preferred Experience:
  • 5+ years of overall experience on semiconductor design field
  • 2+ years of DFT design background.
  • Familiar with yield improvement.
  • Post-Silicon (ATE) pattern debug.
  • Knowledge of synthesis, timing closure and constraints definition is a plus.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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