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Verification Staff Engineer

hace 3 meses

Guadalajara, Jalisco, México Synopsys A tiempo completo

Verification Staff Engineer


Job Description and Requirements

We're not just the world leader in Silicon Design and Verification within the Electronic Design Automation space, but we also have the broadest Silicon IP portfolio in the world that was developed by Synopsys over the last 35+ years. We understand and are experts in the development of SoC's and provide solutions to the world of our customers leveraging Synopsys solutions to deliver worldclass products.

At Synopsys, we are at the heart of innovation that changes the way we work and play. Self-driving cars. Artificial Intelligence. The Cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you

Our Digital Team is looking for a skilled Design Verification Engineer to join our talented team.
If you are an experienced verification designer eager to collaborate with experts in a dynamic digital design team using the latest process technologies and tools, this is the perfect opportunity for you

In this role you will be responsible for understanding the specifications, developing test benches and verifying integrated IP Subsystems for advanced systems and working on solving problems of diverse scope in the verification field with the possibility to be involved on FPGA based prototyping/emulation of complex SoCs

Requirements
Possesses a solid understanding of design SoC specifications, define the verification scope, develop test plans, tests cases, and the verification infrastructure along with ability to verify the correctness of the design. Resolves issues in creative ways. Exercises autonomous judgment in selecting methods and techniques to obtain solutions. Executes projects from start to completion. Contributes to moderately complex aspects of a project. Establishes and develops recommendations to solutions. Works on team-energized or task-oriented projects. May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.
With your design verification experience and applying industry leading methods with state-of-the-art tools, you will take on the challenge of conceptualizing, planning, developing, and executing test environments that wring out even the most difficult design bugs. Exposure to a wide variety of technologies and solutions provides an endless stream of complex new and exciting design verification experiences.

Key Qualifications

  • Bachelor or Master Degree in Electrical, Computer Engineering, Computer Science or related area
  • +5 years of experience verifying SoC devices with an understanding of the overall SoC development design flow process.
  • Demonstrated experience in UVM methodology-based design verification
  • Hands on experience in System Verilog, HDL and scripting languages such as Perl, Python
  • Understand standard protocols such as PCIe, DDR4, GDDR, HBM, AMBA are preferred
  • Knowledge and experience on design validation with Emulation, HAPs or FPGA prototyping system from RTL design is a plus
Capabilities
  • Understand Object-Oriented Programming
  • Participate as a key contributor
  • Create and execute against test plans with an understanding of RTL design
  • Understand and apply modern verification processes and flows in different environments, methods, standards, and experienced with tools such as Synopsys VCS and Verdi
  • Knowledge of FPGA architectures such as Xilinx Virtex/Altera Stratix is a plus
  • Excellent written and verbal communication skills
  • Team player
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.