Analog IC Layout Engineer
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- Education: Bachelor’s Degree in Information Technologies or related.
- Languages: High level of proficiency in English (speaking, reading, writing) Level: B2, C1, C2,
- Modality: Hybrid Work (Tuesday to Thursday onsite)
- Hiring: 100 % Payroll
- Benefits: Social Insurance (IMSS), 12 Vacation days per year, 15 Days of Christmas Bonus, 25 % Vacation Bonus, Life Insurance.
A hands-on, custom analog layout role, working on production silicon from initial floorplanning through to tape-out, on live, high-volume programs.
Day-to-Day Responsibilities
- Design and implement analog layout for cell and block-level IP
- Floorplan and place devices to meet area, matching, and performance targets
- Route power and sensitive analog signals
- Run and resolve DRC/LVS checks
- Collaborate with circuit designers and verification engineers through to tape-out
Requirements
- +3 years of hands-on experience in analog or mixed-signal IC layout
- Advanced English
- Working knowledge of Cadence Virtuoso Layout Editor, or equivalent full-custom layout tools
- Familiarity with Calibre or PVS verification flows (DRC, LVS, ERC)
- Understanding of submicron process effects (STI, WPE, DFM) and layout matching techniques
- Comfortable working in a hybrid onsite environment, collaborating directly with the local and wider design team.
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