Hsio Test Enginner

**HSIO Test Engineer**

**General Summary**

This position is for the Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip). Engineer will be responsible for characterization and developing cost-effective manufacturing test solution for HSIO (SERDES) for leading-edge SoC products in the most advanced processes. These include but not limited to HSIO PHY testing with automated test equipment (ATE). Main responsibilities includes defining and executing the development of Test methodologies and characterization of High Speed SERDES Interfaces such as PCIe, USB3, UFS,DP, MIPI(DSI,CSI). Engineer will be developing Characterization and Test Plans, identifying DFT and test hardware requirements and developing ATE tests/routines/programs to execute test plans. Engineer will be driving first silicon debug to qualify designs fabricated at external foundries, performing technical data analysis of parametric performance over various operating conditions and configurations, driving failure analysis to completion, analyzing high volume manufacturing yields and driving test time reduction. Engineer with be working with cross-functional teams such as IC Design, Systems Engineering, Process Engineering, Hardware Applications, Customer Engineering across the globe in a time critical environment driving improvements in the yield, test time, and quality. The individual selected for the position should be passionate about delivering quality work products, seek to continually learn about new products as well as essential knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information and assist in conducting specialized analyses (e.g., feasibility studies, signal integrity, teardown analyses).

**Preferred Qualifications**
- English fluent (>95% verbal and written).
- Master's Degree in Electrical/Computer Engineering or related field.
- 3-5 years of Hardware Engineering experience in related areas.
- Knowledge of VLSI, CMOS analog, digital, mixed-signal and semiconductor physics.
- Knowledge of HSIO PHY testing is a plus (eg: SERDES Characterization/Validation, loopback, compliance test on any of the PHYs such PCIe, UFS, USB2/3/4, MIPI CSI/DSI etc).
- Good ASIC device level characterization skills. System level knowledge is a plus.
- Knowledge Advantest 93K test platform is a plus.
- Knowledge of signal integrity is a plus.
- Knowledge of computer programming fundamentals (C/C++/Java/Perl)
- Knowledge in test automation development/scripting/debugging is a plus.
- Strong interpersonal, verbal and written communications skills as well as good organization and documentation skills.
- Strong problem solving & debugging skills. Ability to work independently and with good initiative to overcome technical challenges.

**Minimum Qualifications**
- English fluent (>95% verbal and written).
- Bachelor's degree in Engineering, Computer Science, or related field.
- Able to work independently and with good initiative to overcome technical challenges.
- Strong verbal and written communications skills. Able to organize effectively and document work thoroughly while working with local and remote team.