DRAM Design Senior Layout Engineer

hace 3 días

Tlaquepaque, Jalisco, México Micron A tiempo completo
About the Role

We are seeking a highly skilled Senior Layout Engineer to join our DRAM and Emerging Memory Group (DEG) at Micron Technology, Inc.

Your primary responsibility will be to design and develop IP layouts used in DRAM chips. You will perform layout verification, quality check, and documentation, ensuring on-time delivery of block-level layouts with acceptable quality.

You will demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in a multiple-project environment.

Additionally, you will guide and lead junior team members in their execution of sub-block-level layouts and review their work. You will contribute to effective project management, plan and document your layout, and present material for global teams to review.

You will optimally connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.

Requirements
  • Must have 5+ years of experience in layout designs in advanced CMOS processes.
  • Should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.
  • Should have expertise in layout area and routing optimization, design rules, yield, and reliability issues.
  • Good understanding of layout fundamentals, such as electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
  • Should have adequate knowledge of schematics, interface with circuit designers, and CAD teams.
  • Understanding layout effects on circuits, such as speed, capacitance, power, and area, etc.
  • Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layouts.
  • Experience with Cadence tools, including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
  • Should have leadership qualities and be able to do multi-tasking as required.
  • Should be able to work in a team environment and provide technical support to fellow team members.
  • Self-motivated, hardworking, goal-oriented, and excellent verbal and written communication skills.
  • Knowledge of skill coding and layout automation would be a plus.
What We Offer

We offer a competitive salary range of $120,000 - $180,000 per annum, depending on experience, plus benefits including health insurance, retirement plans, and paid time off.

We also offer opportunities for professional growth and development, as well as a dynamic and inclusive work environment.

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