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Design Verification Engineer

hace 2 meses

Tlaquepaque, Jalisco, México Micron A tiempo completo

Job Summary:

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. We're seeking a highly skilled Design Verification Engineer to join our team and contribute to the development of the most advanced DRAM and Emerging memory products.

Key Responsibilities:

  • Develop verification infrastructure and environment to verify probe and burn DFT testmodes functionality.
  • Develop verification infrastructure and environment to port-over the probe and burn DFT patterns into the verification flow.
  • Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
  • Develop SystemVerilog testbench infrastructure (e.g. UVM/Non-UVM and Constrained Random Verification Methodology).
  • Responsible for test plan execution, running regressions, code and functional coverage closure.
  • Assist product engineering teams with circuit and simulation support during post-silicon validation phase.
  • Analyze gaps within the verification flow and methodology and provide solutions to address them.
  • Develop, run, and maintain verification test benches and vectors using industry standard and inhouse developed programs.
  • Write test patterns/vectors and monitors to enhance the functional coverage for all DRAM and Emerging Memory architectures and features.
  • Automate the collection of simulation data through writing software scripts to improve efficiency.
  • Maintain and enhance inhouse developed verification programs and tools.
  • Collaborate closely with international colleagues to develop new verification methodologies and strategies to take on the future challenges in DRAM and Emerging Memory design.

Requirements:

  • BS in Electrical Engineering, Computer Engineering or equivalent with at least 0 - 5 years of industry experience.
  • Deep understanding in CMOS and DRAM circuit design and operation.
  • Familiarity with SystemVerilog testbench/UVM/Constrained Random verification methodology would be a strong plus.
  • Fluent in writing simulation test patterns and vectors.
  • Good debugging and problem-solving skills.
  • Must possess good communication skills and ability to work well in a team environment.
  • Self-driven, dedicated and the ability to multitask.
  • Good programming fundamentals with knowledge in any scripting language.

Preferred Qualifications:

  • Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Familiarity with the DRAM DFT flow and DFT verification.
  • Good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis.
  • Familiarity with digital and analog simulation methodology and tools, i.e. Finesim, Hspice, Hsim, and Verilog.
  • Familiarity with RTL development for logic or mixed-signal circuits.