Innovative Layout Designer for High-Performance Memory Solutions

hace 6 días


Tlaquepaque, Jalisco, México Micron A tiempo completo
Job Overview

We are seeking a skilled and motivated Layout Designer to join our DRAM Engineering Group (DEG) Design Methodology team at Micron Technology.

The successful candidate will play a vital role in creating innovative layouts to support our Commodity, Mobile, and Emerging R&D Design, Process, and Product Engineering customers. This is an excellent opportunity to showcase your expertise in CMOS device physics and electrical characteristics through your exceptional designs and collaborate with local and global teams to ensure quality for Design and Process customers.

Responsibilities
  • Collaborate with Design customers to plan and document layout ensuring it meets Design and Process customer specifications.
  • Verify layout quality using DRC, LVS, and other verification tools, both vendor-supplied and in-house.
  • Apply Design Rules and knowledge of CMOS process in collaboration with Process customers to ensure intended results.
  • Develop and document layout tools and methodologies to enhance quality, either through CAD or coding efforts.
  • Identify issues and provide innovative solutions through effective communication.
Requirements and Qualifications
  • At least 5 + years of experience in custom layout with advanced CMOS process.
  • Expertise in layout area and routing optimization, design rules, yield and reliability issues.
  • Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
  • Adequate knowledge of CMOS circuits/schematics, interface with circuit designer and CAD team.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.
  • Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
  • Leadership qualities and ability to multitask as required.
Preferred Qualifications
  • Experience in Synopsys IC Compiler II or Cadence Innovus.
Education

BS or MS in Electronic/VLSI Engineering or equivalent.

Compensation and Benefits

This position comes with a competitive annual salary range of $120,000-$180,000 depending on qualifications and location. Additionally, we offer a comprehensive benefits package, which includes health insurance, retirement savings plans, paid time off, and opportunities for professional growth and development.



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