Senior Design Engineer

hace 4 semanas


Tlaquepaque, Jalisco, México Micron A tiempo completo
Job Title: Senior Design Engineer - Design Methodology Layout

We are seeking a highly skilled Senior Design Engineer to join our Design Methodology group in the DRAM Engineering Group at Micron Technology. As a Senior Design Engineer, you will play a vital role in creating innovative layouts to support our Commodity, Mobile, and Emerging R&D Design, Process, and Product Engineering customers.

Responsibilities:
  • Plan and document the layout in collaboration with Design customers, ensuring it meets Design and Process customer specifications.
  • Verify layout quality using DRC, LVS, and other verification tools, both vendor-supplied and in-house.
  • Interpret and apply Design Rules, ensuring they are checking as intended, and apply knowledge of CMOS process in collaboration with Process customers.
  • Develop and document layout tools and methodologies to enhance quality, either through CAD or coding efforts.
  • Identify issues and provide innovative solutions through effective communication.
  • Lead sections of the layout design, coordinating with local and global teams to ensure quality for Design and Process customers.
Qualifications & Skills:
  • Must have 5+ years of experience in custom layout with advanced CMOS process.
  • Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.
  • Good understanding of layout fundamentals, including electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
  • Should have adequate knowledge of CMOS circuits/schematics, interface with circuit designer and CAD team.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area, etc.
  • Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.
  • Experience with Cadence tools, including Virtuoso schematic editor, Virtuoso layout, L, XL & Verification tools like Mentor Calibre.
  • Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
  • Should have leadership qualities and able to do multi-tasking as required.
  • Should be able to work in a team environment and able to guide and provide technical support to fellow team members.
  • Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.
  • Knowledge of Skill coding and layout automation is a plus.
  • Preferred Qualifications: Experience in Synopsys IC Compiler II or Cadence Innovus.
  • Education: BS or MS in Electronic/VLSI Engineering or equivalent.


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