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Digital Verification Manager

hace 2 meses

Guadalajara, Jalisco, México Nxp Semiconductors A tiempo completo
About NXP Semiconductors

NXP Semiconductors is a leading global semiconductor company that provides a broad portfolio of differentiated analog, mixed-signal, wireless, and energy management solutions.

We are currently looking for a candidate for a Digital Verification Manager position to manage and drive the digital functional verification team at NXP, Guadalajara.

Key Responsibilities
  • Play a key role in building the Digital Verification team at NXP, Guadalajara.
  • Collaborate with product teams and R&D managers to understand their requirements for verification methodologies, skills, and tools.
  • Train and mentor new hires.
  • Propose hiring needs and grow the Digital Verification team.
  • Be a strong people manager who could motivate and mentor the team members to excel.
  • Be a strong technical lead driving the team's DV execution in an IC development.
Requirements
  • BS/MS in EE and 10+ years of hands-on experience on digital verification methodologies (Metrics Driven Verification, Formal).
  • Strong experience in leading and/or managing verification teams.
  • Ability to drive Verification Plan and DV code reviews.
  • Strong experience writing verification plans, creating test benches, and automating regression test suites.
  • Ability to own, execute and deliver DV coverage closure on an IC or a complex IP. Prior experience in DV technical leadership is strongly preferred.
  • Good understanding in digital RTL debug.
  • Working knowledge of state-of-the-art EDA tools: Cadence Xcelium, Cadence Vmanager, Cadence JasperGold.
  • Strong background in design and verification languages and methodologies (Verilog, SystemVerilog, UVM, SVA).
  • Experience in configuration database management (DesignSync, Git, SVN).
  • Solid scripting skills (Python preferred or Perl or TCL).
  • Good communication skills (English).
Preferred Qualifications
  • Experience with mixed signal (analog, digital) verification methodologies.
  • Experience developing behavioral models for analog IPs (both WREAL or SV RNM).
  • Understand and debug analog schematics.
  • Tools: Cadence Virtuoso, Collabnet, JIRA.