Technical Director, Memory Design Specialist

hace 1 mes

Tlaquepaque, Jalisco, México Micron A tiempo completo

Company Overview

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our mission is to empower our customers' latest and the greatest innovations across a wide spectrum of industries and applications.

About the Role

The Senior Manager of Memory CAD Guadalajara is a technical leadership role within the Engineering Automation (EA) organization at Micron. This position leads the day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to DRAM design teams at the Guadalajara DEG Design Center.

Key Responsibilities

  • Lead the day-to-day support of CAD tools, flows and collateral provided by functionally organized CAD teams worldwide to DRAM design teams at the Guadalajara DEG Design Center.
  • Drive close collaboration with DRAM design, layout, and verification methodology teams to propose and co-develop capabilities outstanding or under supported by EDA vendors and deploy best in class practices and methodologies consistently to DRAM designs worldwide.
  • Drive research and development at the intersection of IC Design Automation and Machine Learning to envision, scope, develop and deliver solutions benefiting IC design.
  • Establish and grow university relationships in the local and regional Guadalajara area to foster partnered research and development in design automation tools with an emphasis on data science and machine learning applications to EDA.

Qualifications

  • Bachelor or preferably Masters/PhD in Computer Engineering, Computer Science or Electrical Engineering.
  • (15-20) + years of direct CAD or Design experience in mixed-signal, custom IC design flows.
  • Experience leading highly technical IC Design or CAD teams distributed worldwide.
  • Familiarity with memory design preferred (DDR3/4/5, LP3/4/5, HBM, NAND).
  • Knowledge of CMOS circuit design, layout and verification, and in-depth experience supporting some of these areas.
  • CMOS transistor level design, logical design and netlisting.
  • CMOS digital and analog layout, Cadence Skill, and parameterized cells.
  • Automated place and route tools.
  • LVS, DRC, LPE flows.
  • ERC flows, static and dynamic circuit checks.
  • Circuit simulation including nanometer scale MOS and interconnect effects.
  • Digital simulation and verification flows (System Verilog/UVM test benches and coverage systems).
  • Power delivery network simulation and analysis.
  • Reliability flows such as HCI, BTI, EM/IR, crosstalk.
  • Mask generation and tape out basics.
  • Experience qualifying vendor tools and internally developed software releases.
  • Experience developing software prototypes for innovative ideas in IC design, layout, and analysis.
  • Experience running agile (software) sprints is a plus.
  • Experience with Machine Learning algorithms and applications.
  • Experience and record of accomplishment delivering production-grade ML applications in IC Design (one or more areas including custom design, layout, logic and timing verification, circuit simulation and physical design verification).
  • Comfortable directing and leading risky/uncertain innovative ML development.
  • Excellent communication and problem-solving skills are required.

Estimated Salary Range: $120,000 - $180,000 per year

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