Advanced CMOS Layout Engineer for DRAM Chips

hace 2 semanas

Tlaquepaque, Jalisco, México Micron A tiempo completo

Company Overview
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever.

Salary
$120,000 - $180,000 per year, depending on qualifications and experience.

Job Description

We are seeking an experienced IP Layout Engineer to join our DRAM and Emerging Memory Group (DEG) at Micron Technology, Inc. As an IP Layout Engineer, you will work with an exceptionally talented team collaborating with peer teams across Micron's global footprint, in a multiple projects-based environment. Your primary responsibilities will include designing and developing IP layouts used in DRAM chips, performing layout verification like LVS/DRC/EM, quality check, and documentation.

Main Responsibilities:

  • Design and development of IP layouts used in DRAM chips.
  • Perform layout verification like LVS/DRC/EM, quality check, and documentation.
  • On-time delivery of block-level layouts with acceptable quality.
  • Demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in a multiple project environment.
  • Guide and lead junior team members in their execution of sub-block-level layouts & review their work.
  • Contribute to effective project management.
  • Plan and document your layout, presenting material for global teams to review.
  • Optimally connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.

Qualifications and Requirements:

  • A minimum of 5 years of experience in layout designs in advanced CMOS process.
  • Ability to perform IP layout development and physical verification activities for complex designs as per provided specifications.
  • Expertise in layout area and routing optimization, design rules, yield, and reliability issues.
  • Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
  • Adequate knowledge of schematics, interface with circuit designer, and CAD team.
  • Understanding layout effects on the circuit such as speed, capacitance, power, and area etc.
  • Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout.
  • Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout, L, XL & Verification tools like Mentor Calibre - Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.
  • Leadership qualities and ability to do multi-tasking as required.
  • Ability to work in a team environment and guide and provide technical support to fellow team members.
  • Self-motivated, hardworking, goal-oriented, and excellent verbal and written communication skills.
  • Knowledge of coding and layout automation would be a plus.

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