Rtl Design and Verification Engineer

A RTL Design and Verification engineering position is available within the Intel Data Center Power Solution group. The Power Solutions group works with Intel silicon, package, and board design teams to deliver leading edge power solutions.

**Your responsibilities will include but not be limited to**:

- RTL design with experience leading implementation of controller for power management ICs.
- Design and Pre-Si verification with experience leading Verilog RTL and model development, prefer experience working with PMIC (Power Management IC's).
- Pre-Si digital verification of power management ICs at system level in emulation.
- Root causing of reported power control issues including RTL implementation, analog models, and specification errors.
- Writing verification plans and documenting models, test benches and maintaining behavioral models, test benches, and test cases in SystemVerilog.
- Leading external suppliers through development of the power management IC RTL.

**Qualifications**:** Minimum qualifications**:
You must possess the below minimum qualifications to be initially considered for this position.

For the following if Bachelor's, minimum of 4+ years of experience, if Master's, minimum of 3+ years of experience, and If PhD's, minimum of 1+ years of experience:

- RTL design and coding expertise using Verilog and/or VHDL for verification and testing digital circuits.
- Developing synthesizable analog models in Pre-Si System on Chip (SoC) and Application Specific Integrated Circuit (ASIC) environments.
- System Verilog and/or Verilog RTL model development.
- Advanced English level.

**Preferred qualifications**:

- Master's, or PhD degree in Electrical Engineering (EE), Computer Science (CS), or related field.
- Experience working with Power Management Integrated Circuits (PMICs) at a system level in emulation and performing digital verification of PMIC's.
- Experience validating externally sourced voltage regulators and PMIC's.
- Experience with I2C, I3C, and Power Management Bus (PMBus) protocols.
- Experience with synthesis and simulation of tool flows.
- Experience in digital design and Pre-Si verification of mixed-signal systems, specifically PMICs.
- Experience in developing synthesizable analog behavioral models representing PMIC behavior in Pre-Si SOC/ASIC environments.
- Experience validating externally sourced voltage regulators and PMICs.

Requirements listed may be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

**Inside this Business Group**:
The Data Platforms Engineering and Architecture (DPEA) Group invents, designs & builds the world's most critical computing platforms which fuel Intel's most important business and solve the world's most fundamental problems. DPEA enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

**Posting Statement**:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

**Benefits**:
**Working Model**:
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
**In certain circumstances the work model may change to accommodate business needs.**
JobType

Hybrid