Lead Analog Layout Engineer for AI/HPC Chips
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Micron Technology is seeking a Layout Build engineer for our DRAM Team in Guadalajara, Mexico. You will lead analog, mixed-signal and full-block layout activities, collaborating with global peers across multiple projects.
Responsibilities include planning, area and time estimation, and ensuring timely delivery of high-quality layouts while applying Cadence VLE/VXL and Mentor Calibre tools to meet stringent design rules and performance goals.
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Guerrero, Guerrero, México 3050 Micron Semiconductor Mexico, S.de R.L. de C.V. Jornada completaMicron Technology, Inc. in Guadalajara, Mexico, invites an experienced Layout Design Engineer to join the HBM team, working on high-performance memory solutions and AI/HPC applications.You will contribute to analog, mixed-signal and full-chip layouts and drive layout verification and effective integration. The role demands 5+ years of layout experience, a BE...
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