Dram Design Senior Layout Engineer

**Our vision is to transform how the world uses information to enrich life for**_all _**.**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.Our team vision is a continuing desire to develop your skills working in a multicultural Team across worldwide geographies Enabling the creative career path you deserve with a collaborative environment and groundbreaking technology and growing upon your imagination and creativity.(Disclaimer): While you may not exhibit all of the characteristics/skills listed below today, we are highly interested in a teammate motivated to grow in both technical and managerial breadth. Suppose you are open to learning, we are determined to help build upon your existing foundation, while rapidly growing your individual, managerial and collaborative skills in this exciting and outstanding opportunity.We are looking for a **DRAM**Layout Engineer**in our **DRAM Engineering Group (DEG)**at **Micron Technology, Inc.**, As a Layout Engineer, you will be working with an exceptionally talented, passionate core team collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment.**Role and Responsibilities**- Responsible for Design and development of IP layouts used in DRAM chips.- Perform layout verification like LVS/DRC/EM, quality check and documentation.- Responsible for on-time delivery of block-level layouts with acceptable quality.- Guide and lead junior team-members in their execution of Sub block-level layouts & review their work.- Plan and document your layout, presenting material for global teams to review- Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project.**Qualification/Requirements**- Must have 5+ years of experience in analog layout designs in CMOS process.- Experience performing IP layout development and physical verification activities for complex designs as per provided specs.- Should have solid knowledge of the layout area and routing optimization, design rules, yield and reliability issues.- Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.- Should have adequate knowledge of schematics, interface with circuit designer and CAD team.- Understanding layout effects on the circuit such as speed, capacitance, power and area.- Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.**Education**BE/BTech or MTech in Electronic/VLSI Engineering or equivalent."The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.