Sr Eng-deg Design Method-layout

**Our vision is to transform how the world uses information to enrich life for **_all_**.**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.**Our vision is to transform how the world uses information to enrich life for **_all_**.**Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.Micron Technology is seeking a skilled and motivated Layout Designer to join our DEG (DRAM Engineering Group) Design Methodology group. As a Layout Designer, you will play a vital role in creating innovative layouts to support our Commodity, Mobile, and Emerging R&D Design, Process, and Product Engineering customers. You will have the opportunity to showcase your expertise in CMOS device physics and electrical characteristics through your exceptional designs, and opportunity to work on mask generation and reticle design.**Responsibilities**:- ** Plan and document** the layout in collaboration with Design customers, ensuring it meets Design and Process customer specifications.- ** Verify layout quality** using DRC, LVS, and other verification tools, both vendor-supplied and in-house.- ** Develop and document** layout tools and methodologies to enhance quality, either through CAD or coding efforts.- ** Identify issues** and provide innovative solutions through effective communication.- ** Lead sections** of the layout design, coordinating with local and global teams to ensure quality for Design and Process customers.**Qualifications & Skills**:- Must have 5 + years of experience in custom layout with advanced CMOS process.- Should have expertise in layout area and routing optimization, design rules, yield and reliability issues.- Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.- Should have adequate knowledge of CMOS circuits/schematics, interface with circuit designer and CAD team.- Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,- Excellent in problem-solving skills in solving area, power, performance and physical verification of custom layout.- Experience with Cadence tools including Virtuoso schematic editor Virtuoso layout L, XL & Verification tools like Mentor Calibre- Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.- Should have leadership qualities and able to do multi-tasking as required.- Should be able to work in a team environment and able to guide and provide technical support to the fellow team members.- Self-motivated, hardworking, goal-oriented and excellent verbal and written communication skills.- Knowledge of Skill coding and layout automation is a plus.**Preferred Qualifications**:- Experience in Synopsys IC Compiler II or Cadence Innovus.**Education**:BS or MS in Electronic/VLSI Engineering or equivalentThe specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position.Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.