Verification Engineer

hace 3 semanas

Guadalajara, México Synopsys A tiempo completo

37070BRMEXICO-Guadalajara**Job Description and Requirements**At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. In addition to the traditional EDA tools and IP we also provide design services to enable our customers with end-to-end SoC design solution in advanced technology nodes. If you share our passion for innovation, we want to meet you.In the role of Verification Engineer you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers.**Key Qualifications**- Bachelor’s Degree in Electrical, Computer Engineering, or Computer Science.- 1+ years of work experience or academic experience in design or verification using hardware description languages.- Knowledge of System Verilog HDL and scripting languages such as Perl, Python, Ruby.- Good Object-Oriented programming background.- Understand standard protocols such as PCIe, DDR4, GDDR, HBM, AMBA are preferred.- Experience in UVM methodology-based verification will be preferred.**Capabilities**- Participate as a key contributor.- Create and execute against verification test plans.Excellent written and verbal communication skills.**Preferred additional experience**- System Verilog/C++ co-simulation.- Overall knowledge of the SoC development process.- RTL design.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.LI-TS1**Job Category**Engineering**Country**Mexico**Job Subcategory**SOC Engineering**Hire Type**Employee

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