Asic Design Verification Engineer

hace 2 semanas

Guadalajara, Jalisco, México INTEL A tiempo completo

In this role, as part of the Media IP and IP Platform development team, you will need to be passionate about developing high-performance IP for HW acceleration of key Cloud, Edge, and Data Center workloads, and engage with the engineering team responsible for architecting and designing the Intel QAT (QuickAssist Technology).

You will have an excellent opportunity to bring to life the next generation Intel IPs for HW acceleration.

In this position you will gain valuable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.


Intel is a Great Place to Work, and is currently defining a new dynamic, flexible and inclusive Future of the Workplace based on three different modes of work: Fully Remote, Hybrid, and On-Site.

We want employees and their managers to partner to determine the work location and model that drives the best results for their type of work.


Responsibilities will include, but are not limited to:

  • Define preSilicon design verification test plans to verify IP/system will meet design requirements.
  • Build testbench components, create tests and sequences for RTL validation.
  • Drive the functional verification of Intel's IPs (Intelectual Property) by working side by side with RTL designers and architects.
  • Analyze RTL tests and waveforms to implement corrective measures on simulation models.
  • Write automation scripts to speed up the team deliveries or avoid repetitive work.

Qualifications:

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or school work/classes/research.

You must possess the below
minimum qualifications to be initially considered for this position:

  • Minimum of 6 months of experience in IP/Block/SOC pre-Si validation with expertise in
    System Verilog and UVM / OVM concepts.
  • Minimum of 6 months of experience with Linux.
  • Intermediate+ English level.
  • Knowledge of ASIC development.
  • Experience working with Media Codecs or encryption/encoding.
  • Knowledge of AMBA AXI/APB protocol.
  • Scripting (Python, Perl, bash script, etc.).

Inside this Business Group:


Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.


Posting Statement:


All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.


Benefits:

Working Model:


This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.


In certain circumstances the work model may change to accommodate business needs.
JobType

Hybrid

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