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Chief Memory Integration Architect

hace 1 mes


Tlaquepaque, Jalisco, México Micron A tiempo completo

**Company Overview**

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At Micron, we're transforming information into intelligence that enriches life for all. As a leader in innovating memory and storage solutions, we accelerate the transformation of information, inspiring the world to learn, communicate, and advance faster than ever.

 

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**Job Description**

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We're seeking a highly motivated Design Verification Engineer to join our innovative and dynamic design and verification team. As a key member of this team, you'll be responsible for evaluating the functionality and performance of Full-chip and block-level circuit designs using various verification tools, techniques, and strategies.

 

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  • Develop verification infrastructure and environment to verify probe and burn DFT test modes functionality.
  • Develop verification infrastructure and environment to port over the probe and burn DFT patterns into the verification flow.
  • Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
  • Develop SystemVerilog testbench infrastructure (e.g. UVM/Non-UVM and Constrained Random Verification Methodology).
  • Responsible for test plan execution, running regressions, code and functional coverage closure.
  • Assist product engineering teams with circuit and simulation support during post-silicon validation phase.
  • Analyze gaps within the verification flow and methodology and provide solutions to address them.
  • Develop, run, and maintain verification test benches and vectors using industry standard and in-house developed programs.
  • Write test patterns/vectors and monitors to enhance the functional coverage for all DRAM and Emerging Memory architectures and features.
  • Automate the collection of simulation data through writing software scripts to improve efficiency.
  • Maintain and enhance in-house developed verification programs and tools.
  • Collaborate closely with international colleagues to develop new verification methodologies and strategies to take on the future challenges in DRAM and Emerging Memory design.
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**Salary Range:** $120,000 - $180,000 per year, depending on qualifications and experience. We offer a competitive salary based on your skills and experience. Our estimated annual compensation range is around $145,000 based on industry standards and considering the role's requirements.