High-Performance DRAM Layout Engineer

hace 2 días

Tlaquepaque, Jalisco, México Micron A tiempo completo

**About Us**

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron and Crucial brands.

Job Summary:

This position will be responsible for translating schematics into layout used for the creation of fabrication reticles. You will be required to meet all engineering and process-related criteria needed for an assigned Dram product.

About the Role

You will be designing and developing IP layouts used in DRAM chips, performing layout verification like LVS/DRC/EM, quality check and documentation. Additionally, you will be responsible for on-time delivery of block-level layouts with acceptable quality.

As a successful candidate, you will demonstrate leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in multiple project environments.

You will guide and lead junior team members in their execution of sub-block-level layouts & review their work. Moreover, you will contribute to effective project management, plan, and document your layout, presenting material for global teams to review.

Furthermore, you will optimally connect with engineering teams in India, Japan, the US, and other global teams to ensure the success of the layout project.

Requirements

To succeed in this role, you must have 3+ years of experience in layout designs in advanced CMOS processes.

You should be able to perform IP layout development and physical verification activities for complex designs as per provided specifications.

A good understanding of layout fundamentals, such as electro-migration, latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc., is essential.

In addition, you should have adequate knowledge of schematics, interface with circuit designers and CAD teams.

You should also understand layout effects on circuits, such as speed, capacitance, power, and area, etc.

An excellent problem-solving skillset is required to solve area, power, performance, and physical verification of custom layouts.

Familiarity with Cadence tools, including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre, is necessary.

Proficiency in device matching, parasitic analysis, electron migration, and isolation techniques is also required.

Leadership qualities and multi-tasking capabilities are essential, along with the ability to work in a team environment and provide technical support to fellow team members.

Self-motivation, hard work, goal-oriented behavior, and excellent verbal and written communication skills are highly valued.

Bonus points for knowledge of skill coding and layout automation.

Educational Requirements

A BE/BTech or MTech in Electronic/VLSI Engineering or equivalent degree is required. We will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.

Compensation Package

The salary range for this position is $120,000 - $180,000 per year.

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