High-Performance DRAM Design Engineer

hace 1 semana

Tlaquepaque, Jalisco, México Micron A tiempo completo
Job Description

We are seeking an experienced DRAM Design Engineer to join our team at Micron, a world leader in innovative memory and storage solutions.

Company Overview

Micron is an industry leader in transforming how the world uses information to enrich life for all. Our relentless focus on customers, technology leadership, and manufacturing and operational excellence drives us to deliver high-performance DRAM, NAND, and NOR memory and storage products through our Micron and Crucial brands.

Our innovations fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities – from the data center to the intelligent edge and across the client and mobile user experience.

Salary and Benefits

The estimated salary for this position is $140,000 per year, based on industry standards and location.

We offer a comprehensive benefits package, including medical, dental, and vision insurance, as well as a 401(k) plan with company match.

Responsibilities

As a DRAM Design Engineer, you will be responsible for translating schematics into layout used for the creation of fabrication reticles. You will meet all engineering and process-related criteria needed for assigned DRAM products and organize logistics and resource allocations to meet scheduled deadlines.

You will also develop methodologies for issue resolution, work with design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits, and understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures.

Required Skills and Qualifications
  • 3+ years of experience in layout designs in advanced CMOS process.
  • Ability to perform IP layout development and physical verification activities for complex designs as per provided specifications.
  • Expertise in layout area and routing optimization, design rules, yield and reliability issues.
  • Good understanding of layout fundamentals i.e. Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc.
  • Adequate knowledge of schematics, interface with circuit designer and CAD team.
  • Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,
  • Excellent problem-solving skills in solving area, power, performance and physical verification of custom layout.
  • Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre.
Education

Bachelor's or Master's degree in Electronic/VLSI Engineering or equivalent; we will also consider exceptionally talented Diploma holders in electronic or VLSI engineering.

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