Memory Verification Architect
hace 14 horas
At Micron, we're pushing the boundaries of memory and storage innovation to transform how the world uses information. With a competitive salary of $150,000 per year, this role offers an exciting opportunity for skilled professionals to join our team as a Chief Verification Architect.
About the RoleThis is a key position in our design and verification team, where you'll work with cutting-edge memory technologies to develop advanced DRAM and Emerging Memory products. Your primary responsibility will be to evaluate the functionality and performance of full-chip and block-level circuit designs using various verification tools, techniques, and strategies.
- Develop verification infrastructure and environment to verify probe and burn DFT testmodes functionality.
- Develop verification infrastructure and environment to port-over the probe and burn DFT patterns into the verification flow.
- Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
- Develop SystemVerilog testbench infrastructure (e.g. UVM/Non-UVM and Constrained Random Verification Methodology).
- Responsible for test plan execution, running regressions, code and functional coverage closure.
- Assist product engineering teams with circuit and simulation support during post-silicon validation phase.
We're looking for individuals with:
- Bachelor's degree in Electrical Engineering, Computer Engineering or equivalent with at least 0-5 years of industry experience.
- Deep understanding in CMOS and DRAM circuit design and operation.
- Familiarity with SystemVerilog testbench/UVM/Constrained Random verification methodology.
- Fluent in writing simulation test patterns and vectors.
- Good debugging and problem-solving skills.
Candidates who possess good communication skills, ability to work well in a team environment, self-driven, dedicated and the ability to multitask will have a strong advantage in this role. Additionally, a good understanding of ASIC design flow including RTL design, verification, logic synthesis, and timing analysis will be highly beneficial.
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