Design Verification Engineer
hace 1 semana
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
We are seeking a highly skilled Design Verification Engineer to join our team. As a key member of our design verification team, you will play a critical role in ensuring the functionality and performance of our advanced DRAM and Emerging memory products.
About the Role
You will be responsible for evaluating the functionality and performance of full-chip and block-level circuit designs using different verification tools, techniques, and strategies. This will include developing verification infrastructure and environment to verify probe and burn DFT testmodes functionality, as well as porting over probe and burn DFT patterns into the verification flow.
You will also provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs. Additionally, you will develop SystemVerilog testbench infrastructure, execute test plans, run regressions, and close code and functional coverage.
Responsibilities
- Develop verification infrastructure and environment to verify probe and burn DFT testmodes functionality.
- Port-over probe and burn DFT patterns into the verification flow.
- Provide verification support to the DRAM and Emerging Memory Design Engineering teams.
- Develop SystemVerilog testbench infrastructure (e.g. UVM/Non-UVM and Constrained Random Verification Methodology).
- Execute test plans, run regressions, and close code and functional coverage.
- Assist product engineering teams with circuit and simulation support during post-silicon validation phase.
- Analyze gaps within the verification flow and methodology and provide solutions to address them.
Requirements
- BS in Electrical Engineering, Computer Engineering or equivalent with at least 3-7 years of industry experience.
- Deep understanding in CMOS and DRAM circuit design and operation.
- Familiarity with SystemVerilog testbench/UVM/Constrained Random verification methodology.
- Fluent in writing simulation test patterns and vectors.
- Good debugging and problem-solving skills.
- Must possess good communication skills and ability to work well in a team environment.
Salary: $120,000 - $180,000 per year, depending on experience.
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