Digital Verification Methodology Lead
hace 4 semanas
Job Summary
Manpower S.A. De C.V is seeking a highly skilled Digital Verification Methodology Lead to join our team in Guadalajara, Mexico. As a key member of our design team, you will be responsible for developing and implementing advanced verification methodologies for memory products.
Key Responsibilities
• Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
• Utilize advanced verification languages and techniques to build a cutting-edge verification platform
• Participate in creating full chip behavior models that are distributed to Micron's worldwide external customers
• Build verification plans incorporating directed and random patterns that cover all features of a memory design
• Perform verification processes with modeling and simulation using industry-standard simulators
• Contribute to cross-group communication to work towards standardization and group success
• Drive innovation into future memory generations within a dynamic work environment
Requirements
• Fluency in verification languages (System Verilog) and methodologies (UVM)
• Solid understanding of object-oriented design
• Ability to abstract complex technical details into an easy-to-understand interface
• Good debugging and problem-solving skills
• Experience in using scripting languages to automate tasks
• Experience defining coverage strategy and writing coverage models
• Must possess good communication skills and ability to work well within and lead a team
• Previous work experience in ASIC or Memory verification
• Good understanding of CMOS circuit design
• Bachelor's or Postgraduate Degree in Electronics Engineering or related engineering field
• 3 to 5 years' experience preferred
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