Senior Memory Verification Expert

hace 2 meses

Tlaquepaque, Jalisco, México Micron A tiempo completo

About the Role

We're seeking a highly skilled Principal Verification Engineer to join our innovative memory verification team at Micron. As a key member of our international team, you will play a crucial role in developing groundbreaking technologies that transform how the world uses information to enrich life.

Key Responsibilities

  • Lead and drive various verification projects and process improvements, including porting probe and burn DFT patterns into the verification flow.
  • Provide verification support to the DRAM and Emerging Memory Design Engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
  • Develop SystemVerilog testbench infrastructure, including UVM and Constrained Random Verification Methodology.
  • Responsible for test plan execution, running regressions, code and functional coverage closure.
  • Assist product engineering teams with circuit and simulation support during post-silicon validation phase.
  • Analyze gaps within the verification flow and methodology, providing solutions to address them.
  • Develop, run, and maintain verification test benches and vectors using industry-standard and in-house developed programs.
  • Write test patterns/vectors and monitors to enhance functional coverage for all DRAM and Emerging Memory architectures and features.
  • Automate the collection of simulation data through writing software scripts to improve efficiency.
  • Maintain and enhance in-house developed verification programs and tools.
  • Collaborate closely with international colleagues to develop new verification methodologies and strategies to tackle future challenges in DRAM and Emerging Memory design.
  • Mentor junior verification engineers.

Requirements

  • BS in Electrical Engineering, Computer Engineering, or equivalent with at least 7 years of industry experience.
  • Deep understanding of CMOS and DRAM circuit design and operation.
  • Familiarity with SystemVerilog testbench/UVM/Constrained Random verification methodology is a strong plus.
  • Fluent in writing simulation test patterns and vectors.
  • Good debugging and problem-solving skills.
  • Must possess good communication skills and the ability to work well in a team environment.
  • Self-driven, dedicated, and the ability to multitask.
  • Good programming fundamentals with knowledge in any scripting language.

What Sets You Apart

  • Previous experience technically leading a team of engineers and mentoring junior engineers is a strong plus.
  • Good understanding of ASIC design flow, including RTL design, verification, logic synthesis, and timing analysis.
  • Familiarity with the DRAM DFT flow and DFT verification.
  • Good understanding of ASIC design flow, including RTL design, verification, logic synthesis, and timing analysis.
  • Familiarity with digital and analog simulation methodology and tools, i.e., Finesim, Hspice, Hsim, and Verilog.
  • Familiarity with RTL development for logic or mixed-signal circuits.

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